M

Mr. Dubey • 100.69K Points
Coach

Q. A user has designed JK flip flop by using the VHDL code. The output is continuously switching between 0 and 1. This condition is known as

  • (A) switching condition
  • (B) master slave condition
  • (C) race around condition
  • (D) edge triggered condition
Share
Explanation by: Mr. Dubey
this continuous switching of output between 0 and 1 may be the result of toggle state of the flip flop. this occurs when both the inputs j and k are high and the output toggles its previous state. this condition is called the race around the condition.

You must be Logged in to update hint/solution

Discusssion

Login to discuss.

Related MCQs

Q. When desk-checking an algorithm, you should set up a table that contains .

Q. What will be the output of the following Python expression? 24//6%3, 24//4//2

Q. A term used to describe interconnected computer configuration is

Q. Add 648 and 487 in BCD code.

Q. Which one of the following is not a structural thing?

Q. What is an equivalence partition (also known as an equivalence class)?

Q. Which of the following register is used in the control unit of the CPU to indicate the next instruction which is to be executed

Q. SGA stands for

Q. ………. sorting is good to use when alphabetizing a large list of names.

Q. Let L = L1 \cap L2, where L1 and L2 are languages as defined below: L1 = {a^{m}b^{m}ca^{n}b^{n} | m, n >= 0 } L2 = {a^{i}b^{j}c^{k} | i, j, k >=

Question analytics