Computer Architecture MCQs | Page - 59

Dear candidates you will find MCQ questions of Computer Architecture here. Learn these questions and prepare yourself for coming examinations and interviews. You can check the right answer of any question by clicking on any option or by clicking view answer button.

📊 Computer Architecture
Q. The number successful accesses to memory stated as a fraction is called as
  • (A) hit rate
  • (B) miss rate
  • (C) success rate
  • (D) access rate
💬 Discuss
✅ Correct Answer: (A) hit rate

Explanation: the hit rate is an important factor in performance measurement.

📊 Computer Architecture
Q. The number failed attempts to access memory, stated in the form of a fraction is called as
  • (A) hit rate
  • (B) miss rate
  • (C) failure rate
  • (D) delay rate
💬 Discuss
✅ Correct Answer: (B) miss rate

Explanation: the miss rate is a key factor in deciding the type of replacement algorithm.

📊 Computer Architecture
Q. In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are incremented by one, when occurs.
  • (A) delay
  • (B) miss
  • (C) hit
  • (D) delayed hit
💬 Discuss
✅ Correct Answer: (B) miss

Explanation: miss usually occurs when the memory block required is not present in the cache.

📊 Computer Architecture
Q. In LRU, the referenced blocks counter is set to’0′ and that of the previous blocks are incremented by one and others remain same, in the case of
  • (A) hit
  • (B) miss
  • (C) delay
  • (D) none of the mentioned
💬 Discuss
✅ Correct Answer: (A) hit

Explanation: if the referenced block is present in the memory it is called as hit.

📊 Computer Architecture
Q. If hit rates are well below 0.9, then they’re called as speedy computers.
  • (A) true
  • (B) false
  • (C) ---
  • (D) ---
💬 Discuss
✅ Correct Answer: (B) false

Explanation: it has to be above 0.9 for speedy computers.

📊 Computer Architecture
Q. The extra time needed to bring the data into memory in case of a miss is called as
  • (A) delay
  • (B) propagation time
  • (C) miss penalty
  • (D) none of the mentioned
💬 Discuss
✅ Correct Answer: (C) miss penalty

Explanation: none.

📊 Computer Architecture
Q. The miss penalty can be reduced by improving the mechanisms for data transfer between the different levels of hierarchy.
  • (A) true
  • (B) false
  • (C) ---
  • (D) ---
💬 Discuss
✅ Correct Answer: (A) true

Explanation: the extra time needed to bring the data into memory in case of a miss is called as miss penalty.

📊 Computer Architecture
Q. The CPU is also called as
  • (A) processor hub
  • (B) isp
  • (C) controller
  • (D) all of the mentioned
💬 Discuss
✅ Correct Answer: (B) isp

Explanation: isp stands for instruction set processor.

📊 Computer Architecture
Q. A common strategy for performance is making various functional units operate parallelly.
  • (A) true
  • (B) false
  • (C) ---
  • (D) ---
💬 Discuss
✅ Correct Answer: (A) true

Explanation: by parallelly accessing data we can have a pipelined processor.

📊 Computer Architecture
Q. The PC gets incremented
  • (A) after the instruction decoding
  • (B) after the ir instruction gets executed
  • (C) after the fetch cycle
  • (D) none of the mentioned
💬 Discuss
✅ Correct Answer: (C) after the fetch cycle

Explanation: the pc always points to the next instruction to be executed.

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