πŸ“Š Computer Architecture
Q. The reason for the implementation of the cache memory is ________
  • (A) To increase the internal memory of the system
  • (B) The difference in speeds of operation of the processor and memory
  • (C) To reduce the memory access and cycle time
  • (D) All of the mentioned
πŸ’¬ Discuss
βœ… Correct Answer: (B) The difference in speeds of operation of the processor and memory
πŸ“Š Computer Architecture
Q. The effectiveness of the cache memory is based on the property of ________
  • (A) Locality of reference
  • (B) Memory localisation
  • (C) Memory size
  • (D) None of the mentioned
πŸ’¬ Discuss
βœ… Correct Answer: (A) Locality of reference
πŸ“Š Computer Architecture
Q. The spatial aspect of the locality of reference means ________
  • (A) That the recently executed instruction is executed again next
  • (B) That the recently executed won’t be executed again
  • (C) That the instruction executed will be executed at a later time
  • (D) That the instruction in close proximity of the instruction executed will be executed in future
πŸ’¬ Discuss
βœ… Correct Answer: (D) That the instruction in close proximity of the instruction executed will be executed in future
πŸ“Š Computer Architecture
Q. The correspondence between the main memory blocks and those in the cache is given by _________
  • (A) Hash function
  • (B) Mapping function
  • (C) Locale function
  • (D) Assign function
πŸ’¬ Discuss
βœ… Correct Answer: (B) Mapping function
πŸ“Š Computer Architecture
Q. The copy-back protocol is used ________
  • (A) To copy the contents of the memory onto the cache
  • (B) To update the contents of the memory from the cache
  • (C) To remove the contents of the cache and push it on to the memory
  • (D) None of the mentioned
πŸ’¬ Discuss
βœ… Correct Answer: (B) To update the contents of the memory from the cache
πŸ“Š Computer Architecture
Q. The address space is 22 bits the memory is 32 bit word addressable what is the memory size
  • (A) 16MB
  • (B) 512KB
  • (C) 4MB
  • (D) 1GB
πŸ’¬ Discuss
βœ… Correct Answer: (A) 16MB
πŸ“Š Computer Architecture
Q. In which cycle the memory is read and the contents of memory at the address containedin the PC register are loaded into in to IR.
  • (A) Execution Cycle
  • (B) Memory Cycle
  • (C) Fetch Cycle
  • (D) Decode Cycle
πŸ’¬ Discuss
βœ… Correct Answer: (C) Fetch Cycle
πŸ“Š Computer Architecture
Q. The part of machine level instruction, which tells the central processor what has to be done, is
  • (A) Operation code
  • (B) Address
  • (C) Locator
  • (D) Flip-Flop
πŸ’¬ Discuss
βœ… Correct Answer: (A) Operation code
πŸ“Š Computer Architecture
Q. ANSI stands for
  • (A) american national standards institute
  • (B) american national standard interface
  • (C) american network standard interfacing
  • (D) american network security interrupt
πŸ’¬ Discuss
βœ… Correct Answer: (A) american national standards institute

Explanation: it is one of the standards of developing a bus.

πŸ“Š Computer Architecture
Q. CISC stands for
  • (A) complete instruction sequential compilation
  • (B) computer integrated sequential compiler
  • (C) complex instruction set computer
  • (D) complex instruction sequential compilation
πŸ’¬ Discuss
βœ… Correct Answer: (C) complex instruction set computer

Explanation: the cisc machines are well adept at handling multiple bus organisation.

Jump to