Computer Architecture MCQs | Page - 65

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M

Mr. Dubey • 100.69K Points
Coach

Q. The reason for the implementation of the cache memory is ________

  • (A) To increase the internal memory of the system
  • (B) The difference in speeds of operation of the processor and memory
  • (C) To reduce the memory access and cycle time
  • (D) All of the mentioned
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M

Mr. Dubey • 100.69K Points
Coach

Q. The effectiveness of the cache memory is based on the property of ________

  • (A) Locality of reference
  • (B) Memory localisation
  • (C) Memory size
  • (D) None of the mentioned
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M

Mr. Dubey • 100.69K Points
Coach

Q. The spatial aspect of the locality of reference means ________

  • (A) That the recently executed instruction is executed again next
  • (B) That the recently executed won’t be executed again
  • (C) That the instruction executed will be executed at a later time
  • (D) That the instruction in close proximity of the instruction executed will be executed in future
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M

Mr. Dubey • 100.69K Points
Coach

Q. The correspondence between the main memory blocks and those in the cache is given by _________

  • (A) Hash function
  • (B) Mapping function
  • (C) Locale function
  • (D) Assign function
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M

Mr. Dubey • 100.69K Points
Coach

Q. The copy-back protocol is used ________

  • (A) To copy the contents of the memory onto the cache
  • (B) To update the contents of the memory from the cache
  • (C) To remove the contents of the cache and push it on to the memory
  • (D) None of the mentioned
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M

Mr. Dubey • 100.69K Points
Coach

Q. The address space is 22 bits the memory is 32 bit word addressable what is the memory size

  • (A) 16MB
  • (B) 512KB
  • (C) 4MB
  • (D) 1GB
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M

Mr. Dubey • 100.69K Points
Coach

Q. In which cycle the memory is read and the contents of memory at the address containedin the PC register are loaded into in to IR.

  • (A) Execution Cycle
  • (B) Memory Cycle
  • (C) Fetch Cycle
  • (D) Decode Cycle
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M

Mr. Dubey • 100.69K Points
Coach

Q. The part of machine level instruction, which tells the central processor what has to be done, is

  • (A) Operation code
  • (B) Address
  • (C) Locator
  • (D) Flip-Flop
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P

Priyanka Tomar • 35.28K Points
Coach

Q. ANSI stands for

  • (A) american national standards institute
  • (B) american national standard interface
  • (C) american network standard interfacing
  • (D) american network security interrupt
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G

Gopal Sharma • 38.32K Points
Coach

Q. CISC stands for

  • (A) complete instruction sequential compilation
  • (B) computer integrated sequential compiler
  • (C) complex instruction set computer
  • (D) complex instruction sequential compilation
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