What parameter causes the main limit on fan-out of CMOS logic in high-speed applications?

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Mr. Dubey

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📊 Digital Electronics and Logic Design

Q. What parameter causes the main limit on fan-out of CMOS logic in high-speed applications?

(A) d.c. input current
(B) output current
(C) input capacitance
(D) power supply voltage.

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✅ Correct Answer: (A) d.c. input current

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