Q. 8: A JK flip-lop has its J input connected to logic level 1 and its input to the Q output. A clock pulse is fed to its clock input. The flip-lop will now

(A) change its state at each clock pulse
(B) go to state 1 and stay there
(C) go to state 0 and stay there
(D) retain its previous state

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✅ Correct Answer: (D) retain its previous state

Published by Mr. Dubey ⭐ 111.54K Points at 16-Sep-2023 03:50 pm in Digital Electronics and Logic Design

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