πŸ“Š Digital Electronics and Logic Design
Q. A J-K lip-lop has its J-input connected to logic level 1 and its input to the Q output pulse is fed to its clock input the flip-flop will now
  • (A) change its state at each clock pulse
  • (B) go to state 1 and stay there
  • (C) go to state 0 and stay there
  • (D) retain its present state
πŸ’¬ Discuss
βœ… Correct Answer: (A) change its state at each clock pulse

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