A pulse train can be delayed by a finite number of clock periods using

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Mr. Dubey

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📊 Digital Electronics and Logic Design

Q. A pulse train can be delayed by a finite number of clock periods using

(A) a serial-in serial-out shift register
(B) a serial-in parallel-out shift register
(C) both (a) and (b)
(D) a parallel- in parallel- out shift register

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✅ Correct Answer: (A) a serial-in serial-out shift register

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