If a clock with time period 'T' is used with n stage shift register, then output of final stage will be delayed by

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Mr. Dubey

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📊 Digital Electronics and Logic Design

Q. If a clock with time period 'T' is used with n stage shift register, then output of final stage will be delayed by

(A) nt sec
(B) (n-1)t sec
(C) n/t sec
(D) (2n+1)t sec

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✅ Correct Answer: (B) (n-1)t sec

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