WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO

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Mr. Dubey

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📊 Digital Electronics and Logic Design

Q. WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO

(A) the flop- flop is triggered
(B) q=0 and q‟=1
(C) q=1 and q’=0
(D) the output of flip- flop remains unchang ed

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✅ Correct Answer: (C) q=1 and q’=0

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