What is an ambiguous condition in a NAND based S’-R’ latch?

M

Mr. Dubey • 52.26K Points
Coach

Q. What is an ambiguous condition in a NAND based S’-R’ latch?

(A) s’=0, r’=1

(B) s’=1, r’=0

(C) s’=1, r’=1

(D) s’=0, r’=0

Correct : Option (D)

Share

Discusssion

Login to discuss.

Related MCQs

Q. In DOWN-counter, each flip-flop is triggered by

Q. ……………….. level is where the model becomes compatible executable code

Q. Survival is approach.

Q. text based browser

Q. Find a counterexample of ∀x∀y(xy > y), where the domain for all variables consists of all integers.

Q. A register is able to hold

Q. A Hamiltonian cycle in a Hamiltonian graph of order 24 has

Q. Which one of the following extends a private network across public networks?

Q. Investment analysis used in neural networks is to predict the movement of_________from previous data.

Q. Which of the following networks supports pipelining effect?