What is one disadvantage of an S-R flip-flop?

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Mr. Dubey

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📊 Digital Logic Circuits (DLC)

Q. What is one disadvantage of an S-R flip-flop?

(A) it has no enable input
(B) it has a race condition
(C) it has no clock input
(D) invalid state

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✅ Correct Answer: (D) invalid state

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