On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when

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Mr. Dubey

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📊 Digital Logic Circuits (DLC)

Q. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when

(A) the clock pulse is low
(B) the clock pulse is high
(C) the clock pulse transitions from low to high
(D) the clock pulse transitions from high to low

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✅ Correct Answer: (C) the clock pulse transitions from low to high

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