Q. The following timing diagram shows flip flop.

  • (A) t flip-flop
  • (B) d flip-flop
  • (C) sr flip-flop
  • (D) jk flip-flop
πŸ’¬ Discuss
βœ… Correct Answer: (B) d flip-flop
Explanation: since there is only one input to the flip flop, therefore, it can be either d or t flip flop. but, the output becomes equal to the input signal as soon as there is a positive edge of the clock therefore, it is a delay flip flop.

Explanation by: Mr. Dubey
since there is only one input to the flip flop, therefore, it can be either d or t flip flop. but, the output becomes equal to the input signal as soon as there is a positive edge of the clock therefore, it is a delay flip flop.

πŸ’¬ Discussion

πŸ“Š Question Analytics

πŸ‘οΈ
174
Total Visits
πŸ“½οΈ
3 y ago
Published
πŸŽ–οΈ
Mr. Dubey
Publisher
πŸ“ˆ
94%
Success Rate