Q. If a clock with time period 'T' is used with n stage shift register, then output of final stage will be delayed by

(A) nt sec
(B) (n-1)t sec
(C) n/t sec
(D) (2n+1)t sec

💬 Discuss

✅ Correct Answer: (B) (n-1)t sec

Published by Gopal Sharma ⭐ 38.32K Points at 08-Feb-2025 08:34 pm in Digital Electronics and Logic Design

You must be Logged in to update hint/solution

💬 Discussion

📊 Question Analytics

👁️

890

Total Visits

📽️

1 y ago

Published

🎖️

Gopal Sharma

Publisher

📈

82%

Success Rate