Q. In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are incremented by one when occurs.

(A) delay
(B) miss
(C) hit
(D) delayed hit

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✅ Correct Answer: (B) miss

Explanation: miss usually occurs when the memory block required is not present in the cache.

Published by Mr. Dubey ⭐ 111.42K Points at 14-Sep-2023 02:43 pm in Computer Architecture

Explanation by: Mr. Dubey

miss usually occurs when the memory block required is not present in the cache.

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