Q. With regard to a D latch
✅ Correct Answer: (C)
the q output follows the d input when en is high
Digital Logic Circuits (DLC) MCQs | Page - 7
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Q. Which of the following is correct for a D latch?
✅ Correct Answer: (B)
q output follows the input d when the enable is high
Q. Which of the following describes the operation of a positive edge-triggered D flip-flop?
✅ Correct Answer: (B)
the output will follow the input on the leading edge of the clock
Q. A positive edge-triggered D flip-flop will store a 1 when
✅ Correct Answer: (B)
the d input is high and the clock transitions from low to high
Q. Why do the D flip-flops receive its designation or nomenclature as ‘Data Flip-flops’?
✅ Correct Answer: (C)
due to its capability to transfer the data into flip-flop
Q. The characteristic equation of D-flip-flop implies that
✅ Correct Answer: (D)
the next state is independent of present state
Q. The asynchronous input can be used to set the flip-flop to the
✅ Correct Answer: (C)
either 1 or 0 state
Q. Input clock of RS flip-flop is given to
✅ Correct Answer: (B)
pulser
Q. D flip-flop is a circuit having
✅ Correct Answer: (C)
4 nand gates
Q. At the end of the clock pulse the value of output Q is uncertain. The situation is referred to as?
✅ Correct Answer: (B)
race around condition
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