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Multi-core Processors MCQs | Page - 1

Dear candidates you will find MCQ questions of Multi-core Processors here. Learn these questions and prepare yourself for coming examinations and interviews. You can check the right answer of any question by clicking on any option or by clicking view answer button.

Q. 1) The idea of cache memory is based           

(A) . on the property of locality of reference
(B) . on the heuristic 90-10 rule
(C) . on the fact that references generally tend to cluster
(D) . all of the above
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Q. 2) Systems that do not have parallel processing capabilities are                         

(A) . sisd
(B) . mimd
(C) . simd
(D) . misd
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Q. 3) Parallel programs: Which speedup could be achieved according to Amdahl´s law for infinite number of processors if 5% of a program is sequential and the remaining part is ideally parallel?

(A) . 10
(B) . 20
(C) . 30
(D) . 40
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Q. 4) In shared bus architecture, the required processor(s) to perform a bus cycle, for fetching data or instructions is                            

(A) . one processor
(B) . two processor
(C) . multi-processor
(D) . none of the above
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Q. 5) Alternative way of a snooping-based coherence protocol, is called a

(A) . write invalidate protocol
(B) . snooping protocol
(C) . directory protocol
(D) . write update protocol
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Q. 6) If no node having a copy of a cache block, this technique is known as           

(A) . cached
(B) . un-cached
(C) . shared data
(D) . valid data
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Q. 7) All nodes in each dimension form a linear array, in the                  .

(A) . star topology
(B) . ring topology
(C) . connect topology
(D) . mesh topology
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Q. 8) tasks being performed in different stages :

(A) . require different amount of time
(B) . require about the same amount of time
(C) . require different amount of time with time difference between any two tasks being same
(D) . require different amount with time difference between any two tasks being different
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Q. 9) The expression 'delayed load' is used in context of

(A) . processor-printer communication
(B) . memory-monitor communication
(C) . pipelining
(D) . none of the above
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Q. 10) During the execution of the instructions, a copy of the instructions is placed in the            .

(A) . register
(B) . ram
(C) . system heap
(D) . cache
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