πŸ“Š Multi-core Processors
Q. The idea of cache memory is based
  • (A) . on the property of locality of reference
  • (B) . on the heuristic 90-10 rule
  • (C) . on the fact that references generally tend to cluster
  • (D) . all of the above
πŸ’¬ Discuss
βœ… Correct Answer: (C) . on the fact that references generally tend to cluster
πŸ“Š Multi-core Processors
Q. Parallel programs: Which speedup could be achieved according to Amdahl´s law for infinite number of processors if 5% of a program is sequential and the remaining part is ideally parallel?
  • (A) . 10
  • (B) . 20
  • (C) . 30
  • (D) . 40
πŸ’¬ Discuss
βœ… Correct Answer: (B) . 20
πŸ“Š Multi-core Processors
Q. In shared bus architecture, the required processor(s) to perform a bus cycle, for fetching data or instructions is
  • (A) . one processor
  • (B) . two processor
  • (C) . multi-processor
  • (D) . none of the above
πŸ’¬ Discuss
βœ… Correct Answer: (C) . multi-processor
πŸ“Š Multi-core Processors
Q. Alternative way of a snooping-based coherence protocol, is called a
  • (A) . write invalidate protocol
  • (B) . snooping protocol
  • (C) . directory protocol
  • (D) . write update protocol
πŸ’¬ Discuss
βœ… Correct Answer: (C) . directory protocol
πŸ“Š Multi-core Processors
Q. If no node having a copy of a cache block, this technique is known as
  • (A) . cached
  • (B) . un-cached
  • (C) . shared data
  • (D) . valid data
πŸ’¬ Discuss
βœ… Correct Answer: (D) . valid data
πŸ“Š Multi-core Processors
Q. All nodes in each dimension form a linear array, in the .
  • (A) . star topology
  • (B) . ring topology
  • (C) . connect topology
  • (D) . mesh topology
πŸ’¬ Discuss
βœ… Correct Answer: (D) . mesh topology
πŸ“Š Multi-core Processors
Q. tasks being performed in different stages :
  • (A) . require different amount of time
  • (B) . require about the same amount of time
  • (C) . require different amount of time with time difference between any two tasks being same
  • (D) . require different amount with time difference between any two tasks being different
πŸ’¬ Discuss
βœ… Correct Answer: (A) . require different amount of time
πŸ“Š Multi-core Processors
Q. The expression 'delayed load' is used in context of
  • (A) . processor-printer communication
  • (B) . memory-monitor communication
  • (C) . pipelining
  • (D) . none of the above
πŸ’¬ Discuss
βœ… Correct Answer: (C) . pipelining
πŸ“Š Multi-core Processors
Q. During the execution of the instructions, a copy of the instructions is placed in the .
  • (A) . register
  • (B) . ram
  • (C) . system heap
  • (D) . cache
πŸ’¬ Discuss
βœ… Correct Answer: (C) . system heap

Jump to