Q 1. Consider a memory organised into 8K rows, and that it takes 4 cycles to complete a read operation. Then the refresh overhead of the chip is
Q 2. The algorithm to remove and place new contents into the cache is called
Q 3. The approach where the memory contents are transferred directly to the processor from the memory is called
Q 4. The correspondence between the main memory blocks and those in the cache is given by
Q 5. The reason for the implementation of the cache memory is
Q 6. The less space consideration as lead to the development of (for large memories).
Q 7. The chip can be disabled or cut off from an external connection using
Q 8. The BUS that allows I/O, memory and Processor to coexist is
Q 9. The transmission on the asynchronous BUS is also called
Q 10. In IBM’s S360/370 systems lines are used to select the I/O devices.