M Mr. Dubey π Coach β 104.60K Points π Basics of Computer Architecture Q. The master indicates that the address is loaded onto the BUS, by activating signal. (A) MSYN (B) SSYN (C) WMFC (D) INTR ποΈ Show Answer π¬ Discuss π Share β‘Menu β Correct Answer: (A) MSYN
M Mr. Dubey π Coach β 104.60K Points π Basics of Computer Architecture Q. Which of the architecture is power efficient? (A) CISC (B) RISC (C) ISA (D) IANA ποΈ Show Answer π¬ Discuss π Share β‘Menu β Correct Answer: (B) RISC
M Mr. Dubey π Coach β 104.60K Points π Basics of Computer Architecture Q. The Sun micro systems processors usually follow architecture. (A) CISC (B) ISA (C) ULTRA SPARC (D) RISC ποΈ Show Answer π¬ Discuss π Share β‘Menu β Correct Answer: (D) RISC
M Mr. Dubey π Coach β 104.60K Points π Basics of Computer Architecture Q. If a processor does not have any stack pointer register, then (A) It cannot have subroutine call instruction (B) It can have subroutine call instruction, but no nested subroutine (C) Nested subroutine calls are possible, but interrupts are not (D) All sequences of subroutine calls and also interrupts are ποΈ Show Answer π¬ Discuss π Share β‘Menu β Correct Answer: (D) All sequences of subroutine calls and also interrupts are
M Mr. Dubey π Coach β 104.60K Points π Basics of Computer Architecture Q. Which of the following register is used in the control unit of the CPU to indicate the next instruction which is to be executed ? (A) Accumulator (B) Index register (C) Instruction decoder (D) Program counter ποΈ Show Answer π¬ Discuss π Share β‘Menu β Correct Answer: (D) Program counter
M Mr. Dubey π Coach β 104.60K Points π Basics of Computer Architecture Q. The addressing mode, where you directly specify the operand value is (A) Immediate (B) Direct (C) Definite (D) Relative ποΈ Show Answer π¬ Discuss π Share β‘Menu β Correct Answer: (A) Immediate
M Mr. Dubey π Coach β 104.60K Points π Basics of Computer Architecture Q. The effective address of the following instruction is MUL 5(R1,R2). (A) 5+R1+R2 (B) 5+(R1*R2) (C) 5+[R1]+[R2] (D) 5*([R1]+[R2]) ποΈ Show Answer π¬ Discuss π Share β‘Menu β Correct Answer: (C) 5+[R1]+[R2]
M Mr. Dubey π Coach β 104.60K Points π Basics of Computer Architecture Q. addressing mode is most suitable to change the normal sequence of execution of instructions. (A) Relative (B) Indirect (C) Index with Offset (D) Immediate ποΈ Show Answer π¬ Discuss π Share β‘Menu β Correct Answer: (A) Relative
M Mr. Dubey π Coach β 104.60K Points π Basics of Computer Architecture Q. The addressing mode which makes use of in-direction pointers is (A) Indirect addressing mode (B) Index addressing mode (C) Relative addressing mode (D) Offset addressing mode ποΈ Show Answer π¬ Discuss π Share β‘Menu β Correct Answer: (A) Indirect addressing mode
M Mr. Dubey π Coach β 104.60K Points π Basics of Computer Architecture Q. In the following indexed addressing mode instruction, MOV 5(R1), LOC the effective address is (A) EA = 5+R1 (B) EA = R1 (C) EA = [R1] (D) EA = 5+[R1] ποΈ Show Answer π¬ Discuss π Share β‘Menu β Correct Answer: (D) EA = 5+[R1]