πŸ“Š Digital Logic Circuits (DLC)
Q. The systematic reduction of logic circuits is accomplished by:
  • (A) symbolic reduction
  • (B) ttl logic
  • (C) using boolean algebra
  • (D) using a truth table
πŸ’¬ Discuss
βœ… Correct Answer: (C) using boolean algebra
πŸ“Š Digital Logic Circuits (DLC)
Q. Each “1” entry in a K-map square represents:
  • (A) a high for each input truth table condition that produces a high output
  • (B) a high output on the truth table for all low input combinations
  • (C) a low output for all possible high input conditions
  • (D) a don’t care condition for all possible input truth table combinations
πŸ’¬ Discuss
βœ… Correct Answer: (A) a high for each input truth table condition that produces a high output
πŸ“Š Digital Logic Circuits (DLC)
Q. Each “0” entry in a K-map square represents:
  • (A) a high for each input truth table condition that produces a high output
  • (B) a high output on the truth table for all low input combinations
  • (C) a low output for all possible high input conditions
  • (D) a don’t care condition for all possible input truth table combinations
πŸ’¬ Discuss
βœ… Correct Answer: (A) a high for each input truth table condition that produces a high output
πŸ“Š Digital Logic Circuits (DLC)
Q. Looping on a K-map always results in the elimination of
  • (A) variables within the loop that appear only in their complemented form
  • (B) variables that remain unchanged within the loop
  • (C) variables within the loop that appear in both complemented and uncomplemented form
  • (D) variables within the loop that appear only in their uncomplemented form
πŸ’¬ Discuss
βœ… Correct Answer: (C) variables within the loop that appear in both complemented and uncomplemented form
πŸ“Š Digital Logic Circuits (DLC)
Q. Which of the following expressions is in the sum-of-products form?
  • (A) (a + b)(c + d)
  • (B) (a * b)(c * d)
  • (C) a* b *(cd)
  • (D) a * b + c * d
πŸ’¬ Discuss
βœ… Correct Answer: (D) a * b + c * d
πŸ“Š Digital Logic Circuits (DLC)
Q. What is an ambiguous condition in a NAND based S’-R’ latch?
  • (A) s’=0, r’=1
  • (B) s’=1, r’=0
  • (C) s’=1, r’=1
  • (D) s’=0, r’=0
πŸ’¬ Discuss
βœ… Correct Answer: (D) s’=0, r’=0
πŸ“Š Digital Logic Circuits (DLC)
Q. A NAND based S’-R’ latch can be converted into S-R latch by placing
  • (A) a d latch at each of its input
  • (B) an inverter at each of its input
  • (C) it can never be converted
  • (D) both a d latch and an inverter at its input
πŸ’¬ Discuss
βœ… Correct Answer: (D) both a d latch and an inverter at its input
πŸ“Š Digital Logic Circuits (DLC)
Q. The difference between a flip-flop & latch is
  • (A) both are same
  • (B) flip-flop consist of an extra output
  • (C) latches has one input but flip-flop has two
  • (D) latch has two inputs but flip-flop has one
πŸ’¬ Discuss
βœ… Correct Answer: (C) latches has one input but flip-flop has two

Jump to