I Indresh Gehalot π Tutor II β 10.11K Points π Computer Architecture Q. The part of machine level instruction, which tells the central processor what has to be done, is (A) Operation code (B) Address (C) Locator (D) Flip-Flop ποΈ Show Answer π¬ Discuss π Share β‘Menu β Correct Answer: (A) Operation code
I Indresh Gehalot π Tutor II β 10.11K Points π Computer Architecture Q. In which cycle the memory is read and the contents of memory at the address containedin the PC register are loaded into in to IR. (A) Execution Cycle (B) Memory Cycle (C) Fetch Cycle (D) Decode Cycle ποΈ Show Answer π¬ Discuss π Share β‘Menu β Correct Answer: (C) Fetch Cycle
I Indresh Gehalot π Tutor II β 10.11K Points π Computer Architecture Q. The address space is 22 bits the memory is 32 bit word addressable what is the memory size (A) 16MB (B) 512KB (C) 4MB (D) 1GB ποΈ Show Answer π¬ Discuss π Share β‘Menu β Correct Answer: (A) 16MB
I Indresh Gehalot π Tutor II β 10.11K Points π Computer Architecture Q. The copy-back protocol is used _______ (A) To copy the contents of the memory onto the cache (B) To update the contents of the memory from the cache (C) To remove the contents of the cache and push it on to the memory (D) None of the mentioned ποΈ Show Answer π¬ Discuss π Share β‘Menu β Correct Answer: (B) To update the contents of the memory from the cache
I Indresh Gehalot π Tutor II β 10.11K Points π Computer Architecture Q. The correspondence between the main memory blocks and those in the cache is given by ________ (A) Hash function (B) Mapping function (C) Locale function (D) Assign function ποΈ Show Answer π¬ Discuss π Share β‘Menu β Correct Answer: (B) Mapping function
I Indresh Gehalot π Tutor II β 10.11K Points π Computer Architecture Q. The spatial aspect of the locality of reference means ______ (A) That the recently executed instruction is executed again next (B) That the recently executed won’t be executed again (C) That the instruction executed will be executed at a later time (D) That the instruction in close proximity of the instruction executed will be executed in future ποΈ Show Answer π¬ Discuss π Share β‘Menu β Correct Answer: (D) That the instruction in close proximity of the instruction executed will be executed in future
I Indresh Gehalot π Tutor II β 10.11K Points π Computer Architecture Q. The effectiveness of the cache memory is based on the property of ______ (A) Locality of reference (B) Memory localisation (C) Memory size (D) None of the mentioned ποΈ Show Answer π¬ Discuss π Share β‘Menu β Correct Answer: (A) Locality of reference
I Indresh Gehalot π Tutor II β 10.11K Points π Computer Architecture Q. The reason for the implementation of the cache memory is _______ (A) To increase the internal memory of the system (B) The difference in speeds of operation of the processor and memory (C) To reduce the memory access and cycle time (D) All of the mentioned ποΈ Show Answer π¬ Discuss π Share β‘Menu β Correct Answer: (B) The difference in speeds of operation of the processor and memory
I Indresh Gehalot π Tutor II β 10.11K Points π Computer Architecture Q. ___ addressing mode is most suitable to change the normal sequence of execution of instructions. (A) Relative (B) Indirect (C) Index with Offset (D) Immediate ποΈ Show Answer π¬ Discuss π Share β‘Menu β Correct Answer: (A) Relative
I Indresh Gehalot π Tutor II β 10.11K Points π Computer Architecture Q. The addressing mode/s, which uses the PC instead of a general purpose register is _____ (A) Indexed with offset (B) Relative (C) direct (D) both Indexed with offset and direct ποΈ Show Answer π¬ Discuss π Share β‘Menu β Correct Answer: (B) Relative