I Indresh Gehalot π Tutor II β 10.11K Points π Computer Architecture Q. The addressing mode which makes use of in-direction pointers is ___ (A) Indirect addressing mode (B) Index addressing mode (C) Relative addressing mode (D) Offset addressing mode ποΈ Show Answer π¬ Discuss π Share β‘Menu β Correct Answer: (A) Indirect addressing mode
I Indresh Gehalot π Tutor II β 10.11K Points π Computer Architecture Q. In the case of, Zero-address instruction method the operands are stored in __ (A) Registers (B) Accumulators (C) Push down stack (D) Cache ποΈ Show Answer π¬ Discuss π Share β‘Menu β Correct Answer: (C) Push down stack
I Indresh Gehalot π Tutor II β 10.11K Points π Computer Architecture Q. The instruction, Add #45, R1 does _____ (A) Adds the value of 45 to the address of R1 and stores 45 in that address (B) Adds 45 to the value of R1 and stores it in R1 (C) Finds the memory location 45 and adds that content to that of R1 (D) None of the mentioned ποΈ Show Answer π¬ Discuss π Share β‘Menu β Correct Answer: (B) Adds 45 to the value of R1 and stores it in R1
I Indresh Gehalot π Tutor II β 10.11K Points π Computer Architecture Q. The method which offers higher speeds of I/O transfers is _________ (A) Interrupts (B) Memory mapping (C) Program-controlled I/O (D) DMA ποΈ Show Answer π¬ Discuss π Share β‘Menu β Correct Answer: (D) DMA
I Indresh Gehalot π Tutor II β 10.11K Points π Computer Architecture Q. To overcome the lag in the operating speeds of the I/O device and the processor we use ______ (A) Buffer spaces (B) Status flags (C) Interrupt signals (D) Exceptions ποΈ Show Answer π¬ Discuss π Share β‘Menu β Correct Answer: (B) Status flags
I Indresh Gehalot π Tutor II β 10.11K Points π Computer Architecture Q. The system is notified of a read or write operation by _________ (A) Appending an extra bit of the address (B) Enabling the read or write bits of the devices (C) Raising an appropriate interrupt signal (D) Sending a special signal along the BUS ποΈ Show Answer π¬ Discuss π Share β‘Menu β Correct Answer: (D) Sending a special signal along the BUS
I Indresh Gehalot π Tutor II β 10.11K Points π Computer Architecture Q. The advantage of I/O mapped devices to memory mapped is _______ (A) The former offers faster transfer of data (B) The devices connected using I/O mapping have a bigger buffer space (C) The devices have to deal with fewer address lines (D) No advantage as such ποΈ Show Answer π¬ Discuss π Share β‘Menu β Correct Answer: (C) The devices have to deal with fewer address lines
I Indresh Gehalot π Tutor II β 10.11K Points π Computer Architecture Q. The usual implementation of the carry circuit involves ______ (A) And & or gates (B) XOR (C) NAND (D) XNOR ποΈ Show Answer π¬ Discuss π Share β‘Menu β Correct Answer: (B) XOR
I Indresh Gehalot π Tutor II β 10.11K Points π Computer Architecture Q. In full adders the sum circuit is implemented using _______ (A) And & or gates (B) NAND gate (C) XOR (D) XNOR ποΈ Show Answer π¬ Discuss π Share β‘Menu β Correct Answer: (C) XOR
I Indresh Gehalot π Tutor II β 10.11K Points π Computer Architecture Q. Which option is true regarding the carry in the ripple adders? (A) Are generated at the beginning only (B) Must travel through the configuration (C) Is generated at the end of each operation (D) None of the mentioned ποΈ Show Answer π¬ Discuss π Share β‘Menu β Correct Answer: (B) Must travel through the configuration