Explanation: the above two methods of mapping the decision of which block to be removed rests with the cache controller.
Computer Architecture MCQs and Notes
Q. In set associative and associative mapping there exists less flexibility.
β
Correct Answer: (B)
false
Q. In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are incremented by one when occurs.
β
Correct Answer: (B)
miss
Explanation: miss usually occurs when the memory block required is not present in the cache.
Q. The directly mapped cache no replacement algorithm is required.
β
Correct Answer: (A)
true
Explanation: the position of each block is pre-determined in the direct mapped cache, hence no need for replacement.
Q. Highly encoded schemes that use compact codes to specify a small number of functions in each micro instruction is
β
Correct Answer: (B)
vertical organisation
Q. The signals are grouped such that mutually exclusive signals are put together.
β
Correct Answer: (A)
true
Explanation: this is done to improve the efficiency of the controller.
Q. To increase the speed of memory access in pipelining, we make use of _____
β
Correct Answer: (C)
Cache
Q. Each stage in pipelining should be completed within ____ cycle.
β
Correct Answer: (A)
1
Q. The fetch and execution cycles are interleaved with the help of _____
β
Correct Answer: (B)
Clock
Q. _____ has been developed specifically for pipelined systems.
β
Correct Answer: (C)
Optimizing compilers
Q. ______ is used to detect and correct the errors that may occur during data transfers.
β
Correct Answer: (A)
ecc
Explanation: ecc stands for error correcting code.